The present invention relates to analog-to-digital converters and particularly to pipelined analog-to-digital converters with low power supply voltages.
Background: Analog to Digital Conversion
Analog to digital conversion is the process of converting an analog data signal, which is most commonly represented as voltage, into a digital format. Determining a digital value which represents a particular analog input is known as "quantization". Serial, delta-sigma or oversampling, parallel, and pipelined are some of the many different analog to digital conversion architectures which exist. Different architectures are suited to different needs.
Serial analog to digital architecture offers a wide range of performance in analog to digital conversion, from low power and low resolution to quantizations with very high resolutions. Serial architecture typically quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution will take N cycles to fully quantize. Delta-sigma analog to digital architecture is used in audio signal processing. The architecture is designed to translate high-speed, low-resolution samples into higher-resolution, lower-speed output. This process is also referred to as oversampling because more samples of the analog data are quantized than actually become output.
By contrast, parallel analog to digital architecture provides the fastest quantization rate per analog signal. In the parallel (or "flash") architecture, a digital value per cycle is produced for each analog data sample, without regard to N, the number of bits of resolution. Parallel architecture requires that all quantization levels be simultaneously compared to the analog signal. This results in the use of 2.sup.N -1 comparators and 2.sup.N +1 resistors to achieve a digital value, with N bits of resolution, per cycle. FIG. 7 depicts a block diagram of a typical comparator configuration for a flash ADC. A three-comparator architecture, for example, will produce a digital output with two bits of resolution. The converter of FIG. 7 employs 2.sup.n -1 latched analog comparators 702 in parallel, where n is the number of bits of resolution. A reference voltage 706 is provided to the comparator bank. A resistive voltage divider 704 provides reference voltages scaled for each of the comparators. The outputs of the comparators are applied to latches controlled by the ENCODE input 714. When the encode command is low (digital "0"), the latches are transparent creating the "track" mode. When the ENCODE input changes to high (digital "1"), the latches go into a "hold" or latched condition, thus freezing the most recent digital outputs of the comparators and applying them to the encoding circuits 710. The signal held in the latches is converted to binary form by the encoders and applied to the output stages 712 as a digital representation of the analog signal 708 which was present at the comparator inputs at the instant the ENCODE command made the change to the "hold" mode.
Background: Pipelined Analog to Digital Architecture
Pipelined analog to digital architecture, like serial analog to digital architecture, is a method of quantizing an analog signal in stages. Algorithms exist for obtaining either 1 or 1.5 bits of resolution per stage. In a 1.5-bit per stage converter, the digital output of each stage is either 1, 0, or -1. In a 1-bit per stage converter, the digital output of each stage is either 1 or -1. For either algorithm, N stages are required for an N-bit digital value. One bit is resolved at each stage with the result and analog signal sample passed along to the next stage for resolution of another bit. In a 1.5 bit per stage converter, the other 1/2 bit in each stage is redundant. Digital correction logic eliminates the redundancy to produce an N bit result. Producing a single digital value for a single analog input requires N cycles, one for each stage. However, the pipelining permits a high degree of parallelism, so that one output per cycle can be produced after the pipeline fills up.
Pipelined analog to digital converters have many applications. They are particularly useful when high speed, high resolution quantization is required. The pipelined analog to digital conversion architecture's ability to meet these demands makes it ideal for high volume telecommunications application such as various digital subscriber lines, digital signal processing at video rates, and for stand alone high speed analog to digital converters.
The advantage of pipelined analog to digital conversion is that each stage of resolution is separated. Once the analog signal is resolved at the first stage and the result passed to the second stage, a new signal can be processed by the first stage. The passing of result and signal from stage to stage continues to stage N at which point a digital value of N bits of resolution can be produced. Quantization of the first signal to N bits of resolution is achieved in N cycles. However, because each stage resolves one bit and passes the result to the next stage, the former stage is free to resolve a bit of the next analog sample.
This staged design allows N analog samples to be in the process of quantization simultaneously. Once the first analog sample is quantized, after N cycles, each successive analog sample is quantized one cycle later. Thus, there is only one cycle delay per digitized signal after the first is fully quantized. Pipelined analog to digital conversion therefore results in the fastest throughput rate of any analog to digital conversion that quantizes one-bit per conversion cycle, as it is capable, after an N-1 cycles start up period, of quantizing one sample per cycle.
Background: Conventional Sub-ADC Solutions
FIG. 2 depicts a block diagram of the analog portion of a pipelined ADC. The pipelined ADC shown in FIG. 2 consists of N consecutive stages. Sub-ADC 202 is a low resolution analog-to-digital converter. Each sub-ADC performs a coarse conversion of its analog input signal to a digital approximation that is used to build the final digital ADC-output. The sub-ADC 202 output is also reconverted to an analog signal and subtracted from the sub-ADC 202 input. The inter-stage amplifier 204 multiplies this difference by a factor r. The amplifier output is be expressed by: EQU V.sub.RES =r(V.sub.IN -d V.sub.REF /2),
where d represents the output of the sub-ADC 202. The multiplication factor, r, is often referred to as the converter radix. A radix of 2 is common for analog-to-digital converter stages of 1 or 1.5 bits per stage. The analog output of each stage is referred to as its residue. The digital output of the overall ADC is constructed by combining the outputs from each of the sub-ADC stages. The digital output is expressed by: EQU D=r.sub.1 r.sub.2 r.sub.3. . . r.sub.N-1 d.sub.1 +r.sub.2 r.sub.3. . . r.sub.n-1 d.sub.1 +. . . +r.sub.N-2 r.sub.N-1 d.sub.1 +r.sub.N-1 d.sub.1
where d.sub.k is the output of the k.sup.th sub-ADC and r.sub.k is the k.sup.th inter-stage amplifier gain.
The particular design choice of the sub-ADC 202 does not necessarily affect the accuracy of the overall ADC. However, the design choice can have a significant affect on the residue signal. This effect on the residue can make optimal performance of the inter-stage amplifier 204 difficult to achieve. The parameters incorporated in the design of a sub-ADC 202 include its output codes, {d.sub.1, d.sub.2, d.sub.3. . . , d.sub.M }, and the transition voltages necessary to produce the output codes, {V.sub.t2, V.sub.t3, V.sub.t4, . . . , V.sub.tM }.
Background: Conventional Three-Comparator Sub-ADC
One commonly used three-comparator sub-ADC has three output codes, {-1, 0, 1}, and two transition voltages, {-V.sub.REF /4, +V.sub.REF /4}. This type of sub-ADC is typically used in CMOS pipelined ADC products. FIG. 3 graphically depicts the quantization law of this two-comparator sub-ADC. FIG. 4 graphically depicts the residue voltage corresponding to the quantization law of the sub-ADC. In both FIGS. 3 and 4 the axes have been normalized for a V.sub.REF of 1. According to FIG. 4, while the-input to the common two-comparator stage is within .+-.3V.sub.REF /4, the voltage residue will nominally be limited to .+-.V.sub.REF /2.
A sub-ADC such as that described above, when used in conjunction with a radix 2 inter-stage amplifier, results in a pipelined ADC stage with several advantages. The most important advantage of such an architecture is that the sub-DAC 206 and inter-stage amplifier 204 can be realized with a simple two-capacitor circuit in a switched capacitor configuration. The layout of the two capacitors can be arranged to eliminate completely the spatial variation of capacitance (that is, the difference in capacitance between nominally equal capacitors due to minor variations in the area of the plates comprising the capacitors). The low amplifier gain of two results in the retention of much of the speed of the amplifier during the amplification phase. Another advantageous attribute of this sub-ADC architecture is that the sub-ADC requires only two comparators. Further, the comparators themselves may possess offsets as large as V.sub.REF /4 without exceeding the analog input range of the next stage.
However, the sub-ADC architecture described above has a major disadvantage. When the input magnitude of the sub-ADC input reaches V.sub.REF (or -V.sub.REF), the inter-stage amplifier output magnitude also becomes V.sub.REF (or -V.sub.REF). Open-loop gain in an operational amp is a function of output voltage with gain being its highest when the output is 0. Also, the accuracy of operational amp output decreases as open-loop gain of the operational amp decreases, resulting in greater residue error. Therefore, a sub-ADC architecture which requires full-scale residue signals, such as the one described above, can make substantially greater demands upon an inter-stage amplifier than one that does not At a full-scale output condition, the open-loop gain of the operational amp will be at its lowest, resulting in the greatest amount of residue error. The architecture described above not only requires full-scale residue signals, but also propagates such full-scale residue signals down the rest of the ADC pipeline. For example, if the initial ADC input, V.sub.IN, is -V.sub.REF, the first sub-ADC stage will produce a digital output of -1, according to the quantization law depicted in FIG. 3, and an analog residue signal error of -V.sub.REF, according to the residue plot of FIG. 4. Additionally, each successive sub-ADC stage will produce the same result, a digital value of -1 and an analog residue signal error of -V.sub.REF. The residue errors of each sub-ADC stage resulting from settling or amplifier finite gain are reproduced and accumulated at every stage.
Pipelined ADC with Relaxed Inter-Stage Amplifier
The present application discloses a pipelined analog-to-digital converter (ADC) architecture that reduces the signal swing of the inter-stage amplifier by a factor of two. Preferably, the first stage of an N-stage pipelined ADC is a three-comparator stage sub-ADC. The successive N-1 stages of the pipelined ADC are each preferably common two-comparator stage sub-ADCs. The nominal residue voltage of the first sub-ADC does not exceed V.sub.REF /2. As input to the next successive sub-ADC, the nominal residue voltage limits the residue error to .+-.V.sub.REF /2. Therefore, the residue error is not propagated and accumulated at each successive sub-ADC stage in the pipeline. The disclosed pipelined ADC requires no more hardware than a traditional two-comparator stage pipelined ADC, which has as its last stage, a three-comparator sub-ADC. Consequently, the disclosed pipelined ADC also requires no additional power consumption over a traditional two-comparator stage pipelined ADC.
An advantage of the present disclosure is the reduction of the signal swing of inter-stage amplifiers by a factor of two. Such a reduction is significant when low power supply voltages limit the output range of operational amplifier.